module sram4K(
  input clk,
  input rst,


  output [5:0] io_sram0_addr,
  output io_sram0_cen,
  output io_sram0_wen,
  output [127:0] io_sram0_wmask,
  output [127:0] io_sram0_wdata,
  input [127:0] io_sram0_rdata,
  
  output [5:0] io_sram1_addr,
  output io_sram1_cen,
  output io_sram1_wen,
  output [127:0] io_sram1_wmask,
  output [127:0] io_sram1_wdata,
  input [127:0] io_sram1_rdata,

  output [5:0] io_sram2_addr,
  output io_sram2_cen,
  output io_sram2_wen,
  output [127:0] io_sram2_wmask,
  output [127:0] io_sram2_wdata,
  input [127:0] io_sram2_rdata,

  output [5:0] io_sram3_addr,
  output io_sram3_cen,
  output io_sram3_wen,
  output [127:0] io_sram3_wmask,
  output [127:0] io_sram3_wdata,
  input [127:0] io_sram3_rdata,

  input wen,
  input [7:0] wstrb,
  input [63:0] wdata,
  input [8:0] addr,
  output [63:0] rdata

  
);
  wire [5:0] paddr = addr[8:3];
  wire [1:0] sel = addr[1:0];
  wire hsb = addr[2];

  wire [63:0] bstrb = {{8{wstrb[7]}},{8{wstrb[6]}},{8{wstrb[5]}},{8{wstrb[4]}},{8{wstrb[3]}},{8{wstrb[2]}},{8{wstrb[1]}},{8{wstrb[0]}}};
  wire [127:0] bwen = (hsb==1'b1)?{bstrb,64'b0}:{64'b0,bstrb};

  wire [127:0] ram_d = (hsb==1'b1)?{wdata,64'b0}:{64'b0,wdata};
  wire [127:0] ram_q[3:0];

  wire [2:0] addr_0;
  Reg #(.WIDTH(3), .RESET_VAL(3'h0)) reg_ram_sel (.clk(clk), .rst(rst), .din(addr[2:0]), .dout(addr_0), .wen(1'b1));
  
  wire [127:0] data = ram_q[addr_0[1:0]];
  assign rdata = (addr_0[2]==1'b1)?data[127:64]:data[63:0];

  
  assign io_sram0_addr = paddr;
  assign io_sram0_cen = ~1'b1;
  assign io_sram0_wen = ~(wen&&(sel==2'd0));
  assign io_sram0_wmask = ~bwen;
  assign io_sram0_wdata = ram_d;
  assign ram_q[0] = io_sram0_rdata;

  assign io_sram1_addr = paddr;
  assign io_sram1_cen = ~1'b1;
  assign io_sram1_wen = ~(wen&&(sel==2'd1));
  assign io_sram1_wmask = ~bwen;
  assign io_sram1_wdata = ram_d;
  assign ram_q[1] = io_sram1_rdata;

  assign io_sram2_addr = paddr;
  assign io_sram2_cen = ~1'b1;
  assign io_sram2_wen = ~(wen&&(sel==2'd2));
  assign io_sram2_wmask = ~bwen;
  assign io_sram2_wdata = ram_d;
  assign ram_q[2] = io_sram2_rdata;

  assign io_sram3_addr = paddr;
  assign io_sram3_cen = ~1'b1;
  assign io_sram3_wen = ~(wen&&(sel==2'd3));
  assign io_sram3_wmask = ~bwen;
  assign io_sram3_wdata = ram_d;
  assign ram_q[3] = io_sram3_rdata;
  
  
  // generate
  //   genvar i;
  //   for (i = 0; i < 4; i = i + 1)
  //   begin : sram4K
  //     S011HD1P_X32Y2D128_BW isnt_S011HD1P_X32Y2D128_BW(
  //       .Q(ram_q[i]),
  //       .CLK(clk),
  //       .CEN(~1'b1),
  //       .WEN(~(wen&&(sel==i))),
  //       .BWEN(~bwen),
  //       .A(paddr),
  //       .D(ram_d)
  //     );
  //   end
  // endgenerate
  

endmodule
